Modern hardware platforms, for example, computing or communication systems, etc., often provide dedicated circuitry to create or collect trace data that is useful for development, debugging, testing and validation purposes. The trace may include a sequence of events that are of interest for some particular purpose. The events may be generated by hardware, firmware or software, including an operating system (OS) that executes on the platform.
These events are typically time-stamped to allow for sequential ordering within the trace. Unfortunately, when a combination of hardware events and OS events are generated, it becomes difficult to assemble a correct event ordering because the OS events are typically stored or buffered by the OS until a convenient time is available to report the results to the trace generating circuitry. The buffer time delay may be very lengthy compared to the timing and acquisition of hardware or firmware events. Additionally, the timestamp for OS events may be generated by a clock associated with the OS which is often independent of the clock used by the trace generating circuitry. This situation increases the difficulty of performing trace debug analysis in applications where the relative timing between hardware and OS events is important.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.